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1

A method of threshold voltage and current gain factor estimation for CMOS IC input transistors

Journal:

Microelectronics Reliability

Year:

1993

Language:

english

File:

PDF, 363 KB

english, 1993

2

Short-channel single-gate SOI MOSFET model

Suzuki, K., Pidin, S.

Journal:

IEEE Transactions on Electron Devices

Year:

2003

Language:

english

File:

PDF, 830 KB

english, 2003

3

Parasitic series resistance extraction and impact ionization current modeling for SOI MOSFETs

S. Pidin, M. Koyanagi

Journal:

Microelectronics Journal

Year:

1998

Language:

english

File:

PDF, 721 KB

english, 1998

4

[IEEE Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. - Honolulu, HI, USA (2004.06.17-2004.06.17)] Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. - MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

Pidin, S., Mori, T., Nakamura, R., Saiki, T., Tanabe, R., Satoh, S., Kase, M., Hashimoto, K., Sugii, T.

Year:

2004

Language:

english

File:

PDF, 184 KB

english, 2004

5

[IEEE 2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, USA (11-13 June 2002)] 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) - Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

Pidin, S., Morisaki, Y., Sugita, Y., Aoyama, T., Irino, K., Nakamura, T., Sugii, T.

Year:

2002

Language:

english

File:

PDF, 231 KB

english, 2002

6

[Japan Soc. Applied Phys 2003 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (10-12 June 2003)] 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) - High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

Goto, K., Tagawa, Y., Ohta, H., Morioka, H., Pidin, S., Momiyama, Y., Okabe, K., Kokura, H., Inagaki, S., Kikuchi, Y., Kase, M., Hashimoto, K., Kojima, M., Sugii, T.

Year:

2003

Language:

english

File:

PDF, 185 KB

english, 2003

7

[IEEE IEEE International Electron Devices Meeting 2003 - Washington, DC, USA (8-10 Dec. 2003)] IEEE International Electron Devices Meeting 2003 - High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Goto, K., Tagawa, Y., Ohta, H., Morioka, H., Pidin, S., Momiyama, Y., Kokura, H., Inagaki, S., Tamura, N., Hori, M., Mori, T., Kase, M., Hashimoto, K., Kojima, M., Sugii, T.

Year:

2003

Language:

english

File:

PDF, 237 KB

english, 2003

8

[IEEE 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. - Honolulu, HI, USA (June 13-15, 2006)] 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. - High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

Shima, M., Okabe, K., Yamaguchi, A., Sakoda, T., Kawamura, K., Pidin, S., Okuno, M., Owada, T., Sugimoto, K., Ogura, J., Kokura, H., Morioka, H., Watanabe, T., Isome, T., Okoshi, K., Mori, T., Hayami,

Year:

2006

Language:

english

File:

PDF, 385 KB

english, 2006

9

[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Experimental and simulation study on sub-50 nm CMOS design

Pidin, S., Shido, H., Yamamoto, T., Horiguchi, N., Kurata, H., Sugii, T.

Year:

2001

Language:

english

File:

PDF, 210 KB

english, 2001

10

[IEEE International Electron Devices Meeting. Technical Digest. IEDM - San Francisco, CA, USA (10-13 Dec. 2000)] International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) - A notched metal gate MOSFET for sub-0.1 μm operation

Pidin, S., Mushiga, M., Shido, H., Yamamoto, T., Sambonsugi, Y., Tamura, Y., Sugii, T.

Year:

2000

Language:

english

File:

PDF, 334 KB

english, 2000

11

[IEEE IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - San Francisco, CA, USA (Dec. 13-15, 2004)] IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

Pidin, S., Mori, T., Inoue, K., Fukuta, S., Itoh, N., Mutoh, E., Obkoshi, K., Nakamura, R., Kobayashi, K., Kawamura, K., Saiki, T., Fukuyama, S., Satoh, S., Kase, M., Hashimoto, K.

Year:

2004

Language:

english

File:

PDF, 258 KB

english, 2004

12

New Analytical Model for Subthreshold Current in Short-Channel Fully-Depleted SOI MOSFETs

Pidin, Sergey, Koyanagi, Mitsumasa

Journal:

Japanese Journal of Applied Physics

Year:

1998

File:

PDF, 1.07 MB

1998

13

Development of Real-Time Microvision System Based on Three-Dimensional LSI Technology

Yu, K.-H., Kudoh, Y., Matsumoto, T., Pidin, S., Koyanagi, M.

Journal:

Journal of Intelligent Material Systems and Structures

Year:

1996

File:

PDF, 562 KB

1996

14

New Electrically Thinned Intrinsic-Channel SOI MOSFET with 0.01 µm Channel Length

T. Shimatani, S. Pidin, M. Koyanagi

Year:

1997

File:

PDF, 774 KB

1997

15

Two-Dimensional Analytical Subthreshold Model and Optimal Scaling of Fully-Depleted SOI MOSFET Down to 0.1 µm Channel Length

Pidin, Sergey, Koyanagi, Mitsumasa

Journal:

Japanese Journal of Applied Physics

Year:

1997

File:

PDF, 1.09 MB

1997

16

Doping process issues for Sub-0.1 μm generation MOSFETs

Sugii, Toshihiro, Pidin, Sergey, Momiyama, Youichi, Goto, Ken- ichi, Tanaka, Takuji, Yamamoto, Tomonari, Futatugi, Toshirou, Kase, Masatak

Journal:

MRS Proceedings

Year:

2001

Language:

english

File:

PDF, 1.13 MB

english, 2001

17

An Analytical Model for the Effective Drive Current in CMOS Circuits

Journal:

IEEE Transactions on Electron Devices

Year:

2018

Language:

english

File:

PDF, 2.06 MB

english, 2018